The present invention relates to a semiconductor integrated circuit device serving as a semiconductor memory device such as a large-capacity dynamic random access memory (DRAM) and the like, and more particularly, to related techniques for reducing power consumption of the device.
Conventionally, there exist, as one type of semiconductor integrated circuit devices, semiconductor memory devices such as a DRAM which has as its basic components memory cell arrays each including a plurality of word lines and bit lines intersecting orthogonally and a plurality of dynamic memory cells arranged in a lattice at the intersection points between the word lines and the bit lines. In recent years, DRAMs have been made large in size and highly integrated at rapid pace, and various techniques are being disclosed to accelerate this progress.
A conventional technique on such a DRAM is disclosed, for example, in Japanese Laid-Open Patent Publication No. 8-181292 (hereinafter, referred to as the first prior art). As shown in FIG. 3 of the publication, the DRAM of the first prior art has, as its basic components, unit memory cell arrays each including a plurality of word lines and bit lines intersecting orthogonally and a plurality of dynamic memory cells arranged in a lattice at the intersection points between the word lines and the bit lines. On each of two opposite sides of the unit memory cell array, a sub-word line drive section including unit sub-word line drive circuits is placed. On each of the other two opposite sides thereof, a sense amplifier section including unit amplifier circuits is placed.
As shown in FIG. 6 of the first prior art, the sub-word line drive circuits of which output terminals correspond to even-numbered sub-word lines of the memory cell array are placed on one side of the memory cell array (the lower side as is viewed from FIG. 6). In the illustrated example, the sub-word line drive section includes 256 sub-word line drive circuits. On the opposite side of the memory cell array (the upper side as is viewed from FIG. 6), the sub-word line drive circuits of which output terminals correspond to odd-numbered sub-word lines of the memory cell array are placed. In the illustrated example, the sub-word line drive section includes 256 sub-word line drive circuits. Every four of the 256 sub-word line drive circuits corresponding to even-numbered sub-word lines are commonly connected to one main word line. In the illustrated example, the four sub-word line drive circuits are also sequentially connected with lines for sub-word line drive signals DX40, DX42, DX44, and DX46. Every four of the 256 sub-word line drive circuits corresponding to odd-numbered sub-word lines are commonly connected to one main word line. In the illustrated example, the four sub-word line drive circuits are also sequentially connected with lines for sub-word line drive signals DX41, DX43, DX45, and DX47.
In the DRAM of the first prior art with the above configuration, therefore, a total of 514 sub-word lines in one sub-memory mat are coupled with the corresponding sub-word line drive circuits in two sub-word line drive sections placed on the opposite sides (upper and lower sides as are viewed from the figure) thereof. The respective sub-word line drive circuits are alternately placed on one side or the opposite side (upper or lower side) of the sub-word lines, and a total of eight sub-word line drive circuits are sequentially connected with one common main word line. Thus, in the first prior art, the sub-word line drive circuits are placed at a pitch twice as large as that of the sub-word lines, and the main word lines are placed at a pitch eight times as large as that of the sub-word lines. In this way, the pitches of the sub-word line drive circuits and the complementary main word lines are relaxed.
The first prior art also discloses three examples of specific constitutions and operations of the sub-word line drive circuits in FIGS. 7, 8, and 9 of the publication (partial circuit diagrams with timing charts).
Each sub-word line drive section includes 256 sub-word line drive circuits as described above. Each of the sub-word line drive circuits in the example shown in FIG. 7 includes a p-channel MOS transistor interposed between a corresponding sub-word line drive signal line and sub-word line, and an n-channel MOS transistor interposed between the corresponding sub-word line and the ground potential. The gates of these MOS transistors are connected to an inverted signal line of a corresponding main word line, i.e., an inverted main word line. The sub-word line drive circuit further includes an n-channel MOS transistor arranged in parallel with the p-channel MOS transistor between the sub-word line drive signal line and the sub-word line and connected to a non-inverted main word line at the gate thereof.
The non-inverted main word line is brought to the ground potential VSS when not selected and, when selected, driven to an internal boosted potential VCH, i.e., the active level such as +4 V used as a word line activating potential. The inverted main word line is brought to the internal boosted potential VCH when not selected and driven to the ground potential VSS when selected. The sub-word line drive signal DX40 is brought to the ground potential VSS when not selected and driven to the internal boosted potential VCH when selected. The internal voltage VCH is generated based on a supply voltage VCC, e.g., 3.3 V, by an internal boosted potential generation circuit incorporated in the DRAM, providing a comparatively stable potential of 4 V.
When the non-inverted main word line and the inverted main word line are brought to the respective inactive levels, both MOS transistors interposed between the sub-word line drive signal line and the sub-word line are turned OFF in the sub-word line drive circuit, while the n-channel MOS transistor interposed between the sub-word line and the ground is turned ON. This results in the sub-word line being set to the non-selection level such as the ground potential VSS, irrespective of the level of the sub-word line drive signal DX40. Meanwhile, when the non-inverted main word line and the inverted main word line are brought to the respective active levels, the n-channel MOS transistor interposed between the sub-word line and the ground is turned OFF. Instead, the MOS transistors interposed between the sub-word line drive signal line and the sub-word line are turned ON. This results in that the sub-word line is set to the internal boosted potential VCH when receiving the active level of the sub-word line drive signal DX40, and set to the ground potential VSS when receiving the inactive level thereof.
In the example shown in FIG. 8, each of the sub-word line drive circuits includes a p-channel MOS transistor interposed between a corresponding non-inverted main word line and sub-word line and receives the sub-word line drive signal DX40 at the gate thereof, and n-channel MOS transistors interposed in parallel between the sub-word line and the ground and connected respectively with the sub-word line drive signal line DX40 and the inverted main word line at the gates thereof.
In the example shown in FIG. 9, each of the sub-word line drive circuits includes a p-channel MOS transistor interposed between a corresponding non-inverted sub-word line drive signal line and sub-word line and connected with an inverted main word line at the gate thereof, and n-channel MOS transistors interposed in parallel between the sub-word line and the ground and connected respectively with the inverted main word line and an inverted sub-word line drive signal line at the gates thereof. In this example, the inverted main word line is brought to the internal boosted potential VCH when not selected and brought to the ground potential VSS when selected. The sub-word line drive signal is brought to the ground potential VSS when not selected and driven to the internal boosted potential VCH when selected. The inverted sub-word line drive signal is brought to the internal boosted potential VCH when not selected and brought to the ground potential VSS when selected.
When the inverted main word line is brought to the internal boosted potential VCH, the p-channel MOS transistor interposed between the sub-word line drive signal line and the sub-word line is turned OFF, while the n-channel MOS transistors interposed between the sub-word line and the ground is turned ON in the sub-word line drive circuit. This results in the potential of the sub-word line being set to the non-selection level such as the ground potential VSS, irrespective of the level of the sub-word line drive signal DX40. Meanwhile, when the inverted main word line is brought to the active level, the n-channel MOS transistor connected with the inverted main word line at the gate thereof is turned OFF in the sub-word line drive circuit. Instead, the p-channel MOS transistor interposed between the sub-word line drive signal line and the sub-word line is turned ON. In this state, when the sub-word line drive signal DX40 is at the internal boosted potential VCH which is the active level, since the inverted sub-word line drive signal is at the ground potential, the n-channel MOS transistor receiving the inverted sub-word line drive signal at the gate thereof is turned OFF. In response to this state, the sub-word line is set to the internal boosted potential VCH. When the sub-word line drive signal is at the ground potential VSS which is the inactive level, since the inverted sub-word line drive signal is at the internal boosted potential VCH, the n-channel MOS transistor receiving the inverted sub-word line drive signal at the gate thereof is turned ON. In response to this state, the sub-word line is set to the ground potential VSS.
The first prior art with the above constitution intends to provide a DRAM and the like taking full advantage of the benefits of the hierarchical structure so as to realize enhanced operation speed, higher degree of circuit integration, and lowered manufacturing cost in the DRAM and the like.
A circuit architecture effective for low power and high speed DRAMs is disclosed, for example, in "Technical Report of IEICE (The Institute of Electronics Information and Communication Engineers)", ICD97-157 (October, 1997), pp. 55-59 (hereinafter, referred to as the second prior art). The literature suggests under Chapter 3.1 a method for reduction of power consumption by a "fish bone layout" of sub-decode lines (sub-word line drive signal lines or inverted sub-word line drive signal lines) in a divided word line (hierarchical word line) architecture.
The technique of the second prior art adopts the divided word line architecture for relaxing the layout pitch of main word lines. In this architecture, a sub-word line is activated when a main word line and a sub-decode line are selected in a sub-decode circuit (sub-word line drive circuit). A fish bone layout is shown in FIG. 3b on page 57 of the literature. As is observed from this figure, only sub-decode lines SDL&lt;0,1&gt; are placed in a sense amplifier section on the left side of a memory cell array as is viewed from the figure. The sub-decode lines SDL&lt;0,1&gt; are not buffered at the intersections with the sub-decode circuits, and connected only with the odd sub-decode circuits, for example. Likewise, only sub-decode lines SDL&lt;2,3&gt; are placed in a sense amplifier section on the right side of the memory cell array. The sub-decode lines SDL&lt;0,1&gt; are not buffered at the intersections with the sub-decode circuits, and connected only with the even sub-decode circuits, for example. With such a hierarchical word line architecture of the fish bone layout, a plurality of sub-decode lines are not driven simultaneously, but driven individually.
Thus, in the second prior art, power reduction is attempted by adopting the hierarchical word line architecture.
However, the above prior art techniques have the following problems.
The hierarchical structures shown in FIGS. 7 and 8 of the first prior art are required to have non-inverted main word lines and inverted main word lines: A total of 64 pairs of non-inverted main word lines and Inverted main word lines have to be arranged alternately over the memory cell array in the illustrated examples. With such a large number of non-inverted main word lines and inverted main word lines alternately arranged over the memory cells, if a defect such as particle attachment occurs during the fabrication process and the like, lines may not be formed as designed, with a possibility that a non-inverted main word line and an inverted main word line may be partly short-circuited with each other. Such non-inverted main word lines and inverted main word lines are generally formed of a comparatively low resistance wiring layer made of metal or the like. In addition, since the non-inverted main word line is at the ground potential VSS and the inverted main word line is at the boosted potential VCH when not selected, a large potential difference is generated therebetween. In view of the above, when not selected, the non-inverted main word line and the inverted main word line may be short-circuited in the state of a large potential difference therebetween and a low resistance, causing markedly large current flow therebetween. This results in failure to satisfy the standby rated current of the product specification and failure to generate a potential as designed in a low-performance boosted potential generation circuit.
The structure shown in FIG. 9 of the first prior art, which includes only non-inverted main word lines arranged over the memory cells, has the following inconvenience.
The inverted main word line is brought to the internal boosted potential VCH when not selected and to the ground potential VSS when selected. The sub-word line drive signal is brought to the ground potential VSS when not selected and to the internal boosted potential VCH when selected. The inverted sub-word line drive signal is brought to the internal boosted potential VCH when not selected and to the ground potential VSS when selected. In other words, the inverted sub-word line drive signal can be considered as a sub-word line non-selection signal that turns the sub-word line to the inactive level by inactivating the sub-word line drive circuit.
When the inverted main word line is turned to the active level, the n-channel MOS transistor connected with the inverted main word line at the gate thereof is turned OFF in the sub-word line drive circuit. Instead, the p-channel MOS transistor interposed between the sub-word line drive signal line and the sub-word line is turned ON. In this state, when the sub-word line drive signal DX40 is at the internal boosted potential VCH which is the active level, since the inverted sub-word line drive signal is at the ground potential, the n-channel MOS transistor receiving the inverted sub-word line drive signal at the gate thereof is turned OFF. In response to this state, the sub-word line is set to the internal boosted potential VCH. When the sub-word line drive signal is at the ground potential VSS which is the inactive level, since the inverted sub-word line drive signal, i.e., the sub-word line non-selection signal is at the internal boosted potential VCH, the n-channel MOS transistor receiving the inverted sub-word line drive signal at the gate thereof is turned ON. In response to this state, the sub-word line is set to the ground potential VSS. Thereby, the inverted sub-word line drive signal, i.e., the sub-word line non-selection signal is charged and discharged between the levels of the boosted potential VCH and the ground potential VSS.
In the above configuration, a total of 256 sub-word line drive circuits are placed in one sub-word line drive section, one-fourth of which, i.e., 64 sub-word line drive circuits, are to receive a common inverted sub-word line drive signal, i.e., a common sub-word line non-selection signal. Moreover, in general, and actually in the first prior art, eight sub-memory mats SMR04 to SMR74, for example, are selected simultaneously, resulting in that nine sub-word line drive sections placed on opposite sides of the selected sub-memory mats operate simultaneously. This means that at least 64.times.9 sub-word line drive circuits operate simultaneously in response to the inverted sub-word line drive signal or the sub-word line non-selection signal. It is the gate electrodes of the n-channel MOS transistors that receive the sub-word line non-selection signal. In the recent miniaturization process, a gate oxide film tends to be thinned. This tends to increase the gate capacitance of a channel MOS transistor. As a result, the total gate capacitance of all the channel MOS transistors that receive the common sub-word line non-selection signal amounts to a significantly large value.
Thus, considering that the total gate capacitance of the plurality of channel MOS transistors that are connected to a common sub-word line non-selection signal to operate simultaneously is significantly large, and moreover that the sub-word line non-selection signal is charged and discharged between a large amplitude of the boosted potential VCH and the ground potential VSS, power consumption of the boosted potential generation circuit greatly increases.
The second prior art disclosed in "Technical Report of IEICE" has the following problems. When the hierarchical word line architecture of the second prior art is adopted and either inverted or non-inverted main word lines are arranged over the memory cells, it is inevitably required to place two kinds of signal lines, i.e., lines for a sub-word line drive signal and lines for a sub-word line non-selection signal, as the sub-word decode lines in the sense amplifier section. This means that two pairs of sub-word line drive signal lines and sub-word line non-selection signal lines (total four lines) must be arranged as the sub-decode lines SDL&lt;0,1&gt; in the sense amplifier section on the left side of the memory cell array. These lines are not buffered at the intersections with the sub-decode circuits, and connected only with the odd sub-decode circuits, for example. Likewise, two pairs of sub-word line drive signal lines and sub-word line non-selection signal lines (total four lines) must be arranged as the sub-decode lines SDL&lt;2,3&gt; in the sense amplifier section on the right side of the memory cell array. These lines are not buffered at the intersections with the sub-decode circuits, and connected only with the even sub-decode circuits, for example. Therefore, in the illustrated example of the fish bone layout hierarchical word line architecture, a pair of sub-word line drive signal line and sub-word line non-selection signal line (total two lines) are driven simultaneously as one sub-decode line.
However, in the fish bone layout hierarchical word line architecture, as in the first prior art, a plurality of sub-word line drive circuits are connected to a common sub-word line non-selection signal line of the sub-decode line. Moreover, in general, and actually in this prior art, a plurality of memory cell mats are selected simultaneously. Accordingly, the sub-word line drive sections on both sides of the memory cell mats are driven simultaneously, and thus a number of sub-word line drive circuits operate simultaneously in response to a sub-word line non-selection signal supplied from the sub-decode line. As described above, the gate electrodes of a large number of n-channel MOS transistors receive the common sub-word line non-selection signal, and a gate oxide film tends to be thinned. As a result, the total gate capacitance of the channel MOS transistors that receive the common sub-word line non-selection signal amounts to a significantly large value. Moreover, the sub-word non-selection signal line is charged and discharged between the boosted potential VCH and the ground potential. This greatly increases power consumption of a boosted potential generation circuit during operation. Furthermore, since the large-capacitance gates of the sub-word line drive circuits in a number of sub-word line drive sections must be charged and discharged using the common sub-word line non-selection signal, a long delay time is required until the potential is established during charging or discharging.
Hereinbelow, the operation of inverting or not inverting main word lines arranged over memory cells will be described using the circuit shown in FIG. 9 of the first prior art (Japanese Laid-Open Patent Publication No. 8-181292) which is generally used as a sub-word line drive circuit.
For example, in selection of a sub-word line, assume the case where the sub-word line drive signal and the sub-word line non-selection signal supplied from a sub-decode line are first turned to the boosted potential VCH as the active level and, after an interval, for example, the inverted main word line is turned to the ground potential VSS as the active level to set the sub-word line to be selected to the boosted potential as the active level. In this case, the p-channel MOS transistor and the n-channel MOS transistor connected to the inverted main word line are turned ON simultaneously when the potential of the inverted main word line shifts from the boosted potential to the ground potential. This causes a current flow through the sub-word line drive circuit from the boosted potential supply terminal to the ground in response to the sub-word line drive signal. This unnecessarily increases power consumption of the boosted potential generation circuit.
In reverse, assume the case where the inverted main word line is first turned to the ground potential VSS as the active level and, after an interval, for example, the sub-word line drive signal and the sub-word line non-selection signal supplied from the sub-decode line are turned to the active level. In this case, while the sub-word line drive signal rises to the boosted potential, the sub-word line non-selection signal falls to the ground potential. During this potential shift, however, large-capacitance gates of channel MOS transistors of the sub-word line drive circuits in a number of sub-word line drive sections are charged and discharged in response to the sub-word line non-selection signal. A long delay time is therefore required until the potential is established during charging or discharging. In other words, it takes a long time to turn OFF the n-channel MOS transistor that operates in response to the sub-word line non-selection signal. At this time, since the inverted main word line is already at the ground potential VSS as the active level, the p-channel MOS transistor connected to the inverted main word line is in the ON state. As a result, a current flows through the sub-word line drive circuit from the boosted potential supply terminal to the ground in response to the sub-word line drive signal. This unnecessarily increases power consumption of the boosted potential generation circuit. Thus, whichever line, the inverted main word line or the sub-decode line (the sub-word line drive signal and the sub-word line non-selection signal), is activated first, power consumption of the boosted potential generation circuit is unnecessarily increased.
In view of the above, in both the first prior art and the second prior art, the boosted potential generation circuit needs a considerably large consumption charge amount compared with the supply charge amount, and becomes large in size requiring a large layout area.